1. Field of the Invention
The present invention relates to a semiconductor device using a dynamically reconfigurable circuit technology.
2. Description of the Related Art
Recently, portable devices that are required to be inexpensive and power-thrifty are also diversifying and supporting more complex functions, and therefore demand higher performance. To simultaneously attain high performance and low power consumption, development of dedicated hardware is inevitable, and the cost of development and manufacturing is growing every year. From this viewpoint, a semiconductor device using a dynamically reconfigurable circuit technology has received a great deal of attention (e.g., “Reconfigurable System”, Ohmsha, pp. 141-208).
A semiconductor device using a dynamically reconfigurable circuit technology is the same as a normal processor which executes an arithmetic process in accordance with instructions given by software but is different in the following points. The semiconductor device using the dynamically reconfigurable circuit technology can read out, from a storage device, a setting of an arithmetic device corresponding to an instruction and change it at the time of operation. The contents of the storage device are dynamically rewritable. The semiconductor device can execute a variety of arithmetic processes in accordance with one instruction by dynamically rewriting a corresponding arithmetic device setting stored in the storage device as needed on the basis of the usage situation. That is, the semiconductor device is different from a normal processor in that the correspondence between instructions and the settings of arithmetic devices is dynamically changeable.
In a normal processor incapable of dynamically changing the settings of arithmetic devices corresponding to instructions, the settings of an arithmetic device are encoded to associate different settings with different instructions. The coded settings are called “instructions”. If the number of kinds of settings that can be implemented by an arithmetic device is increased to improve the performance, the bit width of an instruction increases, and the size of the storage device such as a memory necessary for storing the instructions also increases. This increases the manufacturing cost and power consumption in decoding a coded arithmetic device setting from an instruction.
On the other hand, the semiconductor device using the dynamically reconfigurable circuit technology can dynamically change the correspondence between instructions and the settings of arithmetic devices. The bit width of an instruction necessary for changing a setting of an arithmetic device increases less even when the number of kinds of settings that can be implemented by the arithmetic device increases.
Hence, from the viewpoint of manufacturing cost and power consumption, the semiconductor device using the dynamically reconfigurable circuit technology is assumed as more advantageous than a semiconductor device such as a normal processor with an equivalent processing function.
To further improve the performance of the semiconductor device using the dynamically reconfigurable circuit technology, it is necessary to provide a plurality of arithmetic devices in the semiconductor device and independently control setting change of the arithmetic devices. It is also necessary to enable the transfer of calculated data between the arithmetic devices and a change in settings for data transfer.
Assume such a semiconductor device which executes one arithmetic process by using a plurality of arithmetic devices is like an assembly line. When an arithmetic device is going to transfer the arithmetic result to another arithmetic device, the arithmetic device which should receive the arithmetic result may not be ready for reception. In this case, the arithmetic device which is going to transfer the arithmetic result must stop the process. In addition, all arithmetic devices in the assembly line, which are located before the arithmetic device to be stopped, must also stop the process. This stop process is called a pipeline interlock process.
The conventional semiconductor device using the dynamically reconfigurable circuit technology implements no pipeline interlock mechanism. Instead, the number of arithmetic devices or the number of buffers to be used for data transfer between arithmetic devices is increased to minimize the situations that require the pipeline interlock process even in a complex arithmetic process. A more complex arithmetic process which would inevitably cause a pipeline interlock process is divided into a plurality of arithmetic processes and sequentially executed.
Without the pipeline interlock mechanism, the conventional semiconductor device using the dynamically reconfigurable circuit technology has a problem of high manufacturing cost because of the many arithmetic devices or many buffers necessary for avoiding the pipeline interlock process.
Additionally, if a complex arithmetic process is divided into a plurality of arithmetic processes and sequentially executed to avoid the pipeline interlock process, the arithmetic process becomes inefficient.
To change a complex arithmetic process to a process that requires no pipeline interlock process, arithmetic devices to transfer/receive data may execute a wasteful process irrelevant to the arithmetic process, thereby altering the data transfer/reception timing. However, this method needs extra power consumption for the wasteful arithmetic process and is therefore not adopted by the semiconductor device using the dynamically reconfigurable circuit technology, which is mounted in a device required to be power-thrifty.